VHDL Programming

03VVP02 :: “VHDL & VLSI Programming”
90 Hours Training on “Design Programming & Simulation”
For: – 1st, 2nd, 3rd, 4th year B. E. / B. Tech. (ECE, EE, EEE, EIC, CS, IT, ME, Automobile), M. E./ M. Tech., MCA, BCA, B. Sc. – I. T., M. Sc.,B. Arch., M. Tech. & Professionals.
Topics Cover:-
The training is going to cover & give practical hands on following topics:

Module 1: Digital Electronics Part & Basics

  • Half Adder
  • CMOS Features
  • Types Of ASIC
  • Reconfigurable Logic
  • Combinational Designs
  • Full Adder
  • Multiplexer
  • Demultiplexer
  • Flip Flops
  • Latches
  • Encoder
  • Decoder
  • Universal Gates
  • Conversion (Binary / Decimal / Octal / Hexadecimal )
  • Counters
  • 1’s Complement
  • 2’s Complement
  • Parity Generator
  • Parity Detector
  • Shift Register
  • Frequency Divider Circuit
  • Frequency Multiplier
  • Synchronous And Asynchronous Counter
  • Memory Designing (Ram And Rom)
  • Leading Zero’s And One’s Circuit And Other Sequential Circuit
  • Basic ALU Design
  • Seven Segment Display

Module 2: VHDL Topics

  • Introduction To VHDL Design
  • VHDL Code Structure
  • Future Scope Of VHDL
  • VHDL Input Output Declaration
  • VHDL Used Languages
  • Entity Declaration
  • Architecture Design Process
  • Package Declaration
  • Data Flow Modeling
  • Process Statement
  • If Else Statement
  • Signal Declaration In VHDL
  • Variable Declaration In VHDL
  • For Statement In VHDL
  • Case Statement In VHDL
  • Structural Modeling
  • Program Calling
  • Generic Statement
  • Behavioral Modeling
  • Delay Declaration
  • With Select Statement
  • Wait Statement

Module 3: Programming With Project Navigator

  • Gate (XOR / AND / NAND /NOT / NOR / OR )
  • Half Adder
  • Full Adder
  • Encoder
  • Decoder
  • Multiplexer (2 : 1 / 4 : 1 / 16:1 )
  • Demultiplexer (1:2 / 1:4 / 1:16)
  • Counter (Integer + Binary )
  • D Flip Flop
  • SR Flip Flop
  • JK Flip Flop
  • T Flip Flop
  • Conversion (Integer To Binary , Binary To BCD, Binary To Gray , Binary To Excess -3)
  • Addition ,Subtraction ,Multiplication
  • 4 Bit Addition
  • 4 Bit Subtraction
  • 8*8 Multiplication
  • Programs By Program Calling

Module 4: Software & Hardware

  • Implementation on Model SIM Simulator
  • Implementation on Xilinx Tool
  • Implementation of FPGA

‘Kaizen Tech’ Test & Competition among participants.

Result & Revision.

Conclusion & Videos.

Writing research paper.

IPR.

Projects Cover: -
During this training each and every student is going to design own following projects with their own hands using “FPGA SPARTON-3 Kit”:
1. Digital Clock
a. Integer
b. Binary
2. Traffic Light Controller
3. Multiplication Using Mixed Modeling Style
4. 4 Bit ALU
a. Binary
b. Decimal
5. Multiplication Of Two Floating Point Decimal Numbers
For Students: -

Depth Knowledge of VLSI & VHDL.

Project Discussion and Completion.

CPLD/FPGA Setup is available for Project Demonstration in College.

Interview Preparation.

Full Study Material containing:

  • Software
  • Data Sheet
  • Report Matter
  • Course Layout
  • Project Coverage