Verilog Programming

    03VVP03 :: “Verilog Programming”
    90 Hours Training on “Design Programming & Simulation”
    For: – 1st, 2nd, 3rd, 4th year B. E. / B. Tech. (ECE, EE, EEE, EIC, CS, IT, ME, Automobile), M. E./ M. Tech., MCA, BCA, B. Sc. – I. T., M. Sc.,B. Arch., M. Tech. & Professionals.
    Topics Cover:-
    The training is going to cover & give practical hands on following topics:

    Module 1:- DIGITAL ELECTRONICS TOPICS

  • Half Adder
  • CMOS Features
  • Types Of ASICS
  • Reconfigurable Logic
  • Combinational Designs
  • Full Adder
  • Multiplexer
  • Demultiplexer
  • Flip Flops
  • Latches
  • Encoder
  • Decoder
  • Universal Gates
  • Conversion (Binary / Decimal / Octal / Hexadecimal)
  • Counters
  • 1’s Complement
  • 2’s Complement
  • Parity Generator
  • Parity Detector
  • Shift Register
  • Frequency Divider Circuit
  • Frequency Multiplier
  • Synchronous And Asynchronous Counter
  • Memory Designing (RAM And ROM)
  • Leading Zero’s And One’s Circuit And Other Sequential Circuit
  • Basic ALU Design
  • Seven Segment Display
  • Module 2:- VERILOG Topics

  • Introduction To VERILOG Design
  • VERILOG Code Structure
  • Difference Between VERILOG And VHDL
  • Future Scope Of VERILOG
  • VERILOG Input Output Declaration
  • Data Flow Modeling
  • Always Statement
  • If Else Statement
  • Signal Declaration In VERILOG
  • Variable Declaration In VERILOG
  • For Statement In VERILOG
  • Case Statement In VERILOG
  • Structural Modeling
  • Program Calling
  • Package Declaration
  • Module 3:- Programming Part

  • Gate (XOR/ AND / NAND /NOT / NOR / OR )
  • Half Adder
  • Full Adder
  • Encoder
  • Decoder
  • Multiplexer(2 : 1 / 4 : 1 / 16:1 )
  • Demultiplexer(1:2 / 1:4 / 1:16)
  • Counter (Integer + Binary )
  • D Flip Flop
  • SR Flip Flop
  • JK Flip Flop
  • T Flip Flop
  • Conversion (Integer To Binary, Binary To BCD, Binary To GRAY , Binary To EXCESS -3)
  • Addition, Subtraction, Multiplication
  • 4 Bit Addition
  • 4 Bit Subtraction
  • Module 4:- Hardware At FPGA

  • Sparten 3E [XC3S500] Kit
  • Module 5:- SOFTWARE TOOLS

  • Project Navigator (6.1/10.1)
  • Installed Modelsim
  • ‘Kaizen Tech’ Test & Competition Among Participants.

    Result & Revision.

    Conclusion & Videos.

    Writing Research Paper.

    IPR.

    Projects Cover: -
    During this training each and every student is going to design own following projects with their own hands using “FPGA SPARTON-3 Kit”:
    1. Digital Clock

  • Integer
  • Binary
  • 2. Traffic Light Controller
    3. Code Conversion

  • Binary
  • Octal
  • Hexadecimal
  • Decimal
  • For Students: -

    Depth Knowledge of VLSI & Verilog.

    Project Discussion and Completion.

    CPLD/FPGA Setup is available for Project Demonstration in College.

    Interview Preparation.

    Full Study Material containing:

  • Software
  • Data Sheet
  • Report Matter
  • Course Layout
  • Project Coverage